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psoc ? 4: psoc 4100m family datasheet programmable system-on-chip (psoc ? ) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-96519 rev. *e revised august 19, 2016 general description psoc ? 4 is a scalable and reconfigurable platfo rm architecture for a fami ly of programmable embedde d system controllers with an arm ? cortex?-m0 cpu. it combines programmable and reconfigurable analog and digital blocks with flex ible automatic routing. the psoc 4100m product family, based on this platform architecture, is a combination of a microcont roller with digital programmable logic, programmable analog, programmable interconnect, high-performance analog-to-digital conversion, opamps with comparator mode, and standard communication and timing peripherals. the psoc 4100m products will be fully compatible with members of the psoc 4 platform for new applications and design needs. the programmable analog and digital subsystems allow flexibility and in-field t uning of the design. features 32-bit mcu subsystem 24-mhz arm cortex-m0 cpu wi th single-cycle multiply up to 128 kb of flash with read accelerator up to 16 kb of sram dma engine programmable analog four opamps that operate in deep sleep mode at very low current levels all opamps have reconfigurable high current pin-drive, high-bandwidth internal drive, adc input buffering, and comparator modes with flexible connectivity allowing input connections to any pin four current dacs (idacs) for general-purpose or capacitive sensing applications on any pin two low-power comparators that operate in deep sleep mode 12-bit sar adc with 806-ksps conversion rate low power 1.71 to 5.5 v operation 20-na stop mode with gpio pin wakeup hibernate and deep sleep modes allow wakeup-time versus power trade-offs capacitive sensing cypress capacitive sigma-delta (csd) technique provides best-in-class snr (>5:1) and water tolerance cypress-supplied software component makes capacitive sensing design easy automatic hardware tuning (smartsense?) segment lcd drive lcd drive supported on all pins (common or segment) operates in deep sleep mode with 4 bits per pin memory serial communication four independent run-time reconfigurable serial communication blocks (scb s) with reconfigurable i 2 c, spi, or uart functionality timing and pulse-width modulation eight 16-bit timer/counter pulse-width modulator (tcpwm) blocks center-aligned, edge, and pseudo-random modes comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications package options 68-pin qfn, 64-pin tqfp wide and narrow pitch, and 48-pin and 44-pin tqfp packages up to 55 programmable gpios gpio pins can be capsense, lcd, analog, or digital drive modes, strengths, and slew rates are programmable extended industrial temperature operation ?40 c to +105 c operation psoc creator design environment integrated development environment (ide) provides schematic design entry and build (with analog and digital automatic routing) applications programming interface (api component) for all fixed-function and programmable peripherals industry-standard tool compatibility after schematic entry, development can be done with arm-based industry-stand ard development tools
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 2 of 41 more information cypress provides a wealth of data at www.cypress.com to help you to select the right psoc device for your design, and to help you to quickly and effectively integrate the device into your design. for a comprehensive list of resources, see the knowledge base article kba86521, how to design with psoc 3, psoc 4, and psoc 5lp . following is an abbreviated list for psoc 4: overview: psoc portfolio , psoc roadmap product selectors: psoc 1 , psoc 3 , psoc 4 , psoc 5lp in addition, psoc creator includes a device selection tool. application notes: cypress offers a large number of psoc application notes covering a bro ad range of topics, from basic to advanced level. recommended application notes for getting started with psoc 4 are: ? an79953 : getting started with psoc 4 ? an88619: psoc 4 hardware design considerations ? an86439: using psoc 4 gpio pins ? an57821: mixed signal circuit board layout ? an81623: digital design best practices ? an73854: introduction to bootloaders ? an89610: arm cortex code optimization technical reference manual (trm) is in two documents: ? architecture trm details each psoc 4 functional block. ? registers trm describes each of the psoc 4 registers. development kits: ? cy8ckit-042 , psoc 4 pioneer kit, is an easy-to-use and inexpensive development platform. this kit includes connectors for arduino? compatible shields and digilent? pmod? daughter cards. ? cy8ckit-049 is a very low-cost prototyping platform. it is a low-cost alternative to sampling psoc 4 devices. ? cy8ckit-001 is a common development platform for any one of the psoc 1, psoc 3, psoc 4, or psoc 5lp families of devices. the miniprog3 device provides an interface for flash programming and debug. psoc creator psoc creator is a free windows-based integrated design environment (i de). it enables concurrent hardware and firmware design of psoc 3, psoc 4, and psoc 5lp based systems. create designs usin g classic, familiar schematic capture supported by over 100 pre-verified, production-ready psoc components; see the list of component datasheets . with psoc creator, you can: 1. drag and drop component icons to build your hardware system design in the main design workspace 2. codesign your application firm ware with the psoc hardware, using the psoc creator ide c compiler 3. configure components using the configuration tools 4. explore the library of 100+ components 5. review component datasheets figure 1. multiple-sensor example project in psoc creator
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 3 of 41 contents psoc 4100m block diagram............................................ 4 functional definition........................................................ 5 cpu and memory subsystem ..................................... 5 system resources ...................................................... 5 analog blocks.............................................................. 6 fixed function digital........... ....................................... 7 gpio ........................................................................... 8 special function peripherals... .............. .............. ........ 8 pinouts .............................................................................. 9 power............................................................................... 13 unregulated external supply... .............. .............. ...... 13 regulated external supply........................................ 13 development support .................................................... 14 documentation .......................................................... 14 online ........................................................................ 14 tools.......................................................................... 14 electrical specifications ................................................ 15 absolute maximum ratings..... .................................. 15 device level specifications....................................... 15 analog peripherals .................................................... 19 digital peripherals .... .............. .............. .............. ....... 24 memory ..................................................................... 26 system resources .................................................... 27 ordering information...................................................... 30 part numbering conventions ... ................................. 31 packaging........................................................................ 32 acronyms ........................................................................ 35 document conventions ................................................. 37 units of measure ....................................................... 37 revision history ............................................................. 38 sales, solutions, and legal information ...................... 39 worldwide sales and design supp ort............. .......... 39 products .................................................................... 39 psoc? solutions ...................................................... 39 cypress developer community................................. 39 technical support .................. ................................... 39
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 4 of 41 psoc 4100m block diagram the psoc 4100-m devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. the arm serial_wire debug (swd) interface supports all programming and debug features of the device. complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. it does not require special interfaces, debugging pods, simulators, or emulators. only the standard programming connections are required to fully support debug. the psoc creator integrated development environment (ide) provides fully integrated programming and debug support for psoc 4100-m devices. the swd interface is fully compatible with industry-standard third-party tools. the psoc 4100-m family provides a level of security not possible with multi-chip application solutions or with microcontrollers. this is due to its ability to disable debug features, robust flash protection, and because it allows customer-proprietary functionality to be imple- mented in on-chip programmable blocks. the debug circuits are enabled by default and can only be disabled in firmware. if not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new fi rmware that enables debugging. additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. because all programming, debug, and test inter- faces are disabled when maximum device security is enabled, psoc 4100-m with device security enabled may not be returned for failure analysis. this is a trade-off the psoc 4100-m allows the customer to make. psoc4100m 32-bit ahb-lite deep sleep hibernate active/sleep cpu subsystem sram 16 kb sram controller rom 8 kb rom controller flash 128 kb read accelerator spcif swd/tc nvic, irqmx cortex m0 24 mhz fast mul system interconnect (multi layer ahb) datawire/ dma initiator/mmio io subsystem 49x gpio, 6x gpio_ovt ioss gpio (8x ports) peripherals system resources power clock wdt ilo reset clock control dft logic test imo dft analog sleep control pwrsys ref por lvd nvlatches bod wic reset control xres peripheral interconnect (mmio) pclk 8x tcpwm lcd 4x scb- i2c/spi/uart 2x lp comparator 2x capsense port interface & digital system interconnect (dsi) power modes smx sar adc (12-bit) x1 programmable analog ctbm x2 2x opamp wco high speed i/o matrix
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 5 of 41 functional definition cpu and memory subsystem cpu the cortex-m0 cpu in the psoc 4100-m is part of the 32-bit mcu subsystem, which is opti mized for low-power operation with extensive clock gating. most in structions are 16 bits in length and execute a subset of the thumb-2 instruction set. the cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycl e. it includes a nested vectored interrupt controller (nvic) block with 32 interrupt inputs and also includes a wakeup interrupt controller (wic), which can wake the processor up from the deep sleep mode allowing power to be switched off to the main processor when the chip is in the deep sleep mode. the cortex-m0 cpu provides a non-maskable interrupt (nmi) input, which is made available to the user when it is not in use for system functions requested by the user. the cpu also includes a debug interface, the serial wire debug (swd) interface, which is a 2-wire form of jtag; the debug configuration used for psoc 4100-m has four break-point (address) comparators and two watchpoint (data) comparators. flash the psoc 4100-m has a flash module with a flash accelerator, tightly coupled to the cpu to improve average access times from the flash block. the flash accelerator delivers 85% of single-cycle sram access performance on average. part of the flash module can be used to emulate eeprom operation if required. sram sram memory is retained during hibernate. srom a supervisory rom that contains boot and configuration routines is provided. dma a dma engine, with eight channels, is provided that can do 32-bit transfers and has chainable ping-pong descriptors. system resources power system the power system is described in detail in the section power on page 13 . it provides assurance t hat voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (por), for example) until voltage levels are as required for proper function or generate resets (brown-out detect (bod)) or interrupts (low voltage detect (lvd)). the psoc 4100m operates with a single external supply over the range of 1.71 to 5.5 v and has five different power modes, transi- tions between which are managed by the power system. the psoc 4100m provides sleep, deep sleep, hibernate, and stop low-power modes. clock system the psoc 4100-m clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. in addition, the clock system ensures that no meta-stable conditions occur. the clock system for the psoc 4100-m consists of a watch crystal oscillator (wco) running at 32 khz, the imo (3 to 48 mhz) and the ilo (32-khz nominal) internal oscillators, and provision for an external clock. figure 2. psoc 4100m mcu clocking architecture the clk_hf signal can be divided down to generate synchronous clocks for the analog and digital peripherals. there are a total of 16 clock dividers for the psoc 4100-m, each with 16-bit divide capability. the analog clock leads the digital clocks to allow analog events to occur before digital clock-related noise is generated. the 16-bit capability al lows a lot of flexibility in gener- ating fine-grained frequency values and is fully supported in psoc creator. imo clock source the imo is the primary source of internal clocking in the psoc 4100m. it is trimmed dur ing testing to achieve the specified accuracy. trim values are stored in nonvolatile memory. trimming can also be done on the fly to allow in-field calibration. the imo default frequency is 24 mhz and it can be adjusted between 3 to 48 mhz in steps of 1 mhz. imo tolerance with cypress-provided calibration settings is 2%. ilo clock source the ilo is a very low power oscillator, nominally 32 khz, which is primarily used to generate cl ocks for peripheral operation in deep sleep mode. ilo-driven counters can be calibrated to the imo to improve accuracy. cypress provides a software component, which does the calibration. crystal oscillator the psoc 4100m clock sub system also includes a low-frequency crystal oscillator (3 2-khz wco) that is available during the deep sleep mode and can be used for real-time clock (rtc) and watchdog timer applications. dsi_out[3:0] imo wco ilo clk_ext clk_hf clk_lf dsi_in[3] dsi_in[2] dsi_in[0] dsi_in[1]
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 6 of 41 watchdog timer a watchdog timer is implemented in the clock block running from the low-frequency clock; this allows watchdog operation during deep sleep and generates a watchdog reset or an interrupt if not serviced before the timeout o ccurs. the watchdog reset is recorded in the reset cause register. reset the psoc 4100m can be reset from a variety of sources including a software reset. reset events are asynchronous and guarantee reversion to a known state. the reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. an xres pin is reserved for external reset to avoid complications with configu- ration and multiple pin functions during power-on or reconfigu- ration. voltage reference the psoc 4100m reference system generates all internally required references. a 1% voltage reference spec is provided for the 12-bit adc. to allow better signal-to-noise ratios (snr) and better absolute accuracy, it is possible to add an external bypass capacitor to the internal reference using a gpio pin or to use an external reference for the sar. analog blocks 12-bit sar adc the 12-bit sar adc can operate at a maximum sample rate of 806 ksamples/second. the block functionality is augmented for the user by adding a reference buffer to it (trimmable to 1%) and by providing the choice of three internal voltage references: v dd , v dd /2, and v ref (nominally 1.024 v) as well as an external reference through a gpio pin. the sample-and-hold (s/h) aperture is programmable allowing the gain bandwidth requirements of the amplifier driving the sar inputs, which determine its settling time, to be relaxed if required. the system performance will be 65 db for true 12-bit precision if appropriate references are used and system noise levels permit. to improve performance in noisy conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier. the sar is connected to a fixed set of pins through an 8-input sequencer (expandable to 16 inputs). the sequencer cycles through selected channels autonom ously (sequencer scan) and does so with zero switching ov erhead (that is, the aggregate sampling bandwidth is equal to 1 msps, whether it is for a single channel or distributed over several channels). the sequencer switching is effected through a state machine or through firmware-driven switching. a feat ure provided by the sequencer is buffering of each channel to reduce cpu interrupt service requirements. to accommodate signals with varying source impedance and frequency, it is possible to have different sample times programmable for each channel. in addition, the signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed and the cpu to read the values and check for out-of-range values in software. the sar is able to digitize the output of the on-board temper- ature sensor for calibration and other temperature-dependent functions. the sar is not available in deep sleep and hibernate modes as it requires a high-speed clock. the sar operating range is 1.71 to 5.5 v. figure 3. sar adc system diagram sarmux port 2 (8 inputs) vplus vminus p0 p7 data and status flags reference selection external reference and bypass (optional) pos neg sarseq saradc inputs from other ports vdd/2 vddd vref ahb system bus and programmable logic interconnect sequencing and control
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 7 of 41 analog multiplex bus the psoc 4100m has two concentric analog buses (analog mux bus a and analog mux bus b) that circumnavigate the periphery of the chip. these buses can transport analog signals from any pin to various analog blocks (inc luding the opamps) and to the capsense blocks allowing, for instance, the adc to monitor any pin on the chip. these buses are independent and can also be split into three independent sections. this allows one section to be used for capsense purposes, one for general analog signal processing, and the third for general-purpose digital peripherals and gpio. four opamps the psoc 4100m has four opamps with comparator modes, which allow most common analog functions to be performed on-chip eliminating external components; pgas, voltage buffers, filters, trans-impedance amplif iers, and other functions can be realized with external passives saving power, cost, and space. the on-chip opamps are designed with enough bandwidth to drive the sample-and-hold circuit of the adc without requiring external buffering. the opamps can operate in the deep sleep mode at very low power levels. the following diagram shows one of two identical opamp pairs of the opamp subsystem. figure 4. identical opamp pairs in opamp subsystem the ovals in figure 4 represent analog switches, which may be controlled via user firmware, the sar sequencer, or user-defined programmable logic. the opamps (oa0 and oa1) are configu- rable via these switches to perf orm all standard opamp functions with appropriate feedback components. the opamps (oa0 and oa1) are programmable and reconfigu- rable to provide standard opamp functionality via switchable feedback components, unity gain functionality for driving pins directly, or for internal use (such as buffering sar adc inputs as indicated in the diagram), or as true comparators. the opamp inputs provide highly flexible connectivity and can connect directly to dedicated pins or, via the analog mux buses, to any pin on the chip. analog swit ch connectivity is controllable by user firmware. the opamps operate in deep sleep mode at very low currents allowing analog circuits to remain operational during deep sleep. temperature sensor the psoc 4100m has one on-chip temperature sensor. this consists of a diode, which is bi ased by a current source that can be disabled to save power. the temperature sensor is connected to the adc, which digitizes the reading and produces a temper- ature value using cypress-supplied software that includes calibration and linearization. low-power comparators the psoc 4100m has a pair of low-power comparators, which can also operate in the deep sleep and hibernate modes. this allows the analog syst em blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. the comparator outputs are normally synchronized to avoid meta-stability unless operating in an asynchronous power mode (hibernate) where the system wake-up circuit is activated by a comparator switch event. fixed function digital timer/counter/pwm (tcpwm) block the tcpwm block uses a16-bit counter with user-program- mable period length. there is a capture register to record the count value at the time of an event (which may be an i/o event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate co mpare value signals, which are used as pwm duty cycle outputs. the block also provides true and complementary outputs with programmable offset between them to allow use as deadband programmable complementary pwm outputs. it also has a kill input to force outputs to a prede- termined state; for ex ample, this is used in motor drive systems when an overcurrent state is indicated and the pwms driving the fets need to be shut off immediately with no time for software intervention. the psoc 4100m has eight tcpwm blocks. serial communication blocks (scb) the psoc 4100m has four scbs, wh ich can each implement an i 2 c, uart, or spi interface. i 2 c mode: the hardware i 2 c block implements a full multi-master and slave interface (it is capable of multimaster arbitration). this block is capable of operating at speeds of up to 1 mbps (fast mode plus) and has flexible buffering options to reduce interrupt overhead and latency for the cpu. it also supports ezi 2 c that creates a mailbox address range in the memory of the psoc 4100m and effectively reduces i 2 c commu- nication to reading from and writing to an array in memory. in addition, the block supports an 8-deep fifo for receive and transmit which, by increasing the time given for the cpu to read data, greatly reduces the need for clock stretching caused by the cpu not having read data on time. the fifo mode is available in all channels and is very useful in the absence of dma. the i 2 c peripheral is compatible with the i 2 c standard-mode, fast-mode, and fast-mode plus devices as defined in the nxp i 2 c-bus specification and user manual (um10204). the i 2 c bus i/o is implemented with gpio in open-drain modes. analog mux bus b analog mux bus a internal out0 to sar adc to sar adc 1x oa0 10x internal out1 1x oa 1 10x + - + - p0 p6 p5 p4 p3 p2 p1 p7
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 8 of 41 uart mode: this is a full-feature uart operating at up to 1 mbps. it supports automotive single-wire interface (lin), infrared interface (irda), and smartcard (iso7816) protocols, all of which are minor variants of the basic uart protocol. in addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common rx and tx lines. common uart functions such as parity error, break detect, and frame error are supported. an 8-deep fifo allows much greater cpu service la tencies to be tolerated. spi mode: the spi mode support s full motorola spi, ti ssp (essentially adds a start pulse used to synchronize spi codecs), and national microwire (half-duplex form of spi). the spi block can use the fifo and also supports an ezspi mode in which data interchange is reduced to reading and writing an array in memory. gpio the psoc 4100m has 55 gpios in the 68-pin qfn package. the gpio block implements the following: eight drive strength modes incl uding strong push-pull, resistive pull-up and pull-down, weak (resistive) pull-up and pull-down, open drain and open source, input only, and disabled input threshold select (cmos or lvttl) individual control of input and output disables hold mode for latching previous state (used for retaining i/o state in deep sleep mode and hibernate modes) selectable slew rates for dv/dt related noise control to improve emi the pins are organized in logical entities called ports, which are 8-bit in width. during power-on and reset, t he blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on curre nt. a multiplexing network known as a high-speed i/o matrix is used to multiplex between various signals that may connect to an i/o pin. pin locations for fixed-function peripherals are also fixed to reduce internal multi- plexing complexity. data output and pin state register s store, respectively, the values to be driven on the pins and the states of the pins themselves. every i/o pin can generate an interrupt if so enabled and each i/o port has an interrupt request (irq) and interrupt service routine (isr) vector associated with it (8 for psoc 4100m). the pins of port 6 (up to 6 depending on the package) are overvoltage tolerant (v in can exceed v dd ). the overvoltage cells will not sink more than 10 a when their inputs exceed v ddio in compliance with i 2 c specifications. special function peripherals lcd segment drive the psoc 4100m has an lcd controller, which can drive up to four commons and up to 51 segments. any pin can be either a common or a segment pin. it uses full digital methods to drive the lcd segments requiring no generation of internal lcd voltages. the two methods used are referred to as digital correlation and pwm. digital correlation pertains to modulating the frequency and levels of the common and segment signals to generate the highest rms voltage across a segment to light it up or to keep the rms signal zero. this method is good for stn displays but may result in reduced contrast with tn (cheaper) displays. pwm pertains to driving the panel with pwm signals to effec- tively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired lcd voltage. this method results in higher power consumption but can result in better results when driving tn displays. lcd operation is supported during deep sleep refreshing a small display buffer (4 bits; 1 32-bit register per port). capsense capsense is supported on all pins in the psoc 4100m through a capsense sigma-delta (csd) block that can be connected to any pin through an analog mux bus that any gpio pin can be connected to via an analog switch. capsense functionality can thus be provided on any pin or group of pins in a system under software control. a component is provided for the capsense block, which provides automat ic hardware tuning (cypress smartsense?), to make it easy for the user. shield voltage can be driven on another mux bus to provide water tolerance capability. water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. each csd block has two idacs which can be used for general purposes if capsense is not being used.(both idacs are available in that case) or if capsense is used without water tolerance (one idac is available). the psoc 4100m has two csd blocks which can be used independently; one for capsense and the other for idacs. the two capsense blocks are refe rred to as csd0 and csd1. capacitance sensing inputs on ports 0, 1, 2, 3, 4, 6, and 7 are sensed by csd0. capacitance sensing inputs on port 5 are sensed by csd1.
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 9 of 41 pinouts the following is the pin list for the psoc 4100m. this shows the po wer supply and port pins (for example, p0.0 is pin 0 of port 0). 68-qfn 64-tqfp 48-tqfp 44-tqfp pin name pin name pin name pin name 42 p0.0 39 p0.0 28 p0.0 24 p0.0 43 p0.1 40 p0.1 29 p0.1 25 p0.1 44 p0.2 41 p0.2 30 p0.2 26 p0.2 45 p0.3 42 p0.3 31 p0.3 27 p0.3 46 p0.4 43 p0.4 32 p0.4 28 p0.4 47 p0.5 44 p0.5 33 p0.5 29 p0.5 48 p0.6 45 p0.6 34 p0.6 30 p0.6 49 p0.7 46 p0.7 35 p0.7 31 p0.7 50 xres 47 xres 36 xres 32 xres 51 vccd 48 vccd 37 vccd 33 vccd 52 vssd 49 vssd 38 vssd dn vssd 53 vddd 50 vddd 39 vddd 34 vddd 40 vdda 35 vdda 54 p5.0 51 p5.0 55 p5.1 52 p5.1 56 p5.2 53 p5.2 57 p5.3 54 p5.3 58 p5.4 59 p5.5 55 p5.5 60 vdda 56 vdda 40 vdda 35 vdda 61 vssa 57 vssa 41 vssa 36 vssa 62 p1.0 58 p1.0 42 p1.0 37 p1.0 63 p1.1 59 p1.1 43 p1.1 38 p1.1 64 p1.2 60 p1.2 44 p1.2 39 p1.2 65 p1.3 61 p1.3 45 p1.3 40 p1.3 66 p1.4 62 p1.4 46 p1.4 41 p1.4 67 p1.5 63 p1.5 47 p1.5 42 p1.5 68 p1.6 64 p1.6 48 p1.6 43 p1.6 1 p1.7/vref 1 p1.7/vref 1 p1.7/vref 44 p1.7/vref 1 vssd 2 p2.0 2 p2.0 2 p2.0 2 p2.0 3 p2.1 3 p2.1 3 p2.1 3 p2.1 4 p2.2 4 p2.2 4 p2.2 4 p2.2 5 p2.3 5 p2.3 5 p2.3 5 p2.3 6 p2.4 6 p2.4 6 p2.4 6 p2.4 7 p2.5 7 p2.5 7 p2.5 7 p2.5
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 10 of 41 the pins of port 6 are overvoltage-tolerant. pins 36, 37, and 38 are no-connects on the 68-pin qfn. pins 34, 35, and 36 are no-connects on the 64-pin tqfp. pins 11 and 15 are no-connect s in the 48-pin tqfp. all vss pins must be tied together. the output drivers of i/o ports p0 and p7 are connected to vddd. output drivers of i/o ports 1, 2, and 5 are connected to vdda. output drivers of i/o ports 3, 4, and 6 are connected to vddio. 8 p2.6 8 p2.6 8 p2.6 8 p2.6 9 p2.7 9 p2.7 9 p2.7 9 p2.7 10 vssa 10 vssa 10 vssd 10 vssd 11 vdda 11 vdda 12 p6.0 12 p6.0 13 p6.1 13 p6.1 14 p6.2 14 p6.2 15 p6.3 16 p6.4 15 p6.4 17 p6.5 16 p6.5 18 vssio 17 vssio 10 vssd 10 vssd 19 p3.0 18 p3.0 12 p3.0 11 p3.0 20 p3.1 19 p3.1 13 p3.1 12 p3.1 21 p3.2 20 p3.2 14 p3.2 13 p3.2 22 p3.3 21 p3.3 16 p3.3 14 p3.3 23 p3.4 22 p3.4 17 p3.4 15 p3.4 24 p3.5 23 p3.5 18 p3.5 16 p3.5 25 p3.6 24 p3.6 19 p3.6 17 p3.6 26 p3.7 25 p3.7 20 p3.7 18 p3.7 27 vddio 26 vddio 21 vddio 19 vddd 28 p4.0 27 p4.0 22 p4.0 20 p4.0 29 p4.1 28 p4.1 23 p4.1 21 p4.1 30 p4.2 29 p4.2 24 p4.2 22 p4.2 31 p4.3 30 p4.3 25 p4.3 23 p4.3 32 p4.4 31 p4.4 33 p4.5 32 p4.5 34 p4.6 33 p4.6 35 p4.7 39 p7.0 37 p7.0 26 p7.0 40 p7.1 38 p7.1 27 p7.1 41 p7.2 68-qfn 64-tqfp 48-tqfp 44-tqfp pin name pin name pin name pin name
document number: 001-96519 rev. *e page 11 of 41 psoc ? 4: psoc 4100m family datasheet each of the pins shown in the previous table can have multiple programmable functions as shown in the following table. column h eadings refer to analog and alternate pin functions: port/pin analog alt. function 1 alt. function 2 alt. function 3 alt. function 4 alt. function 5 p0.0 lpcomp.in_p[0] scb[0].spi_select1:0 p0.1 lpcomp.in_n[0] scb[0].spi_select2:0 p0.2 lpcomp.in_p[1] scb[0].spi_select3:0 p0.3 lpcomp.in_n[1] p0.4 wco_in scb[1].uart_rx:0 scb[1 ].i2c_scl:0 scb[1].spi_mosi:1 p0.5 wco_out scb[1].uart_tx:0 scb[1 ].i2c_sda:0 scb[1].spi_miso:1 p0.6 ext_clk:0 scb[1].uart_cts:0 scb[1].spi_clk:1 p0.7 scb[1].uart_rts:0 wakeup scb[1].spi_select0:1 p5.0 ctb1.oa0.inp tcpwm.line[4]:2 scb[2].uart_ rx:0 scb[2].i2c_scl:0 scb[2].spi_mosi:0 p5.1 ctb1.oa0.inm tcpwm.line_compl[4]:2 scb[2]. uart_tx:0 scb[2].i2c_sda :0 scb[2].spi_miso:0 p5.2 ctb1.oa0.out tcpwm.line[5]:2 scb[2].uart_cts:0 lpcomp.comp[0]:1 scb[2].spi_clk:0 p5.3 ctb1.oa1.out tcpwm.line_compl[5]:2 scb[2].uar t_rts:0 lpcomp.comp[1]:1 scb[2].spi_select0:0 p5.4 ctb1.oa1.inm tcpwm.line[6]:2 scb[2].spi_select1:0 p5.5 ctb1.oa1.inp tcpwm.line_compl[6]:2 scb[2].spi_select2:0 p5.6 ctb1.oa0.inp_alt tcpwm.line[7]:0 scb[2].spi_select3:0 p5.7 ctb1.oa1.inp_alt tcpwm.line_compl[7]:0 p1.0 ctb0.oa0.inp tcpwm.line[2]:1 scb[0].uart_ rx:1 scb[0].i2c_scl:0 scb[0].spi_mosi:1 p1.1 ctb0.oa0.inm tcpwm.line_compl[2]:1 scb[0]. uart_tx:1 scb[0].i2c_sda :0 scb[0].spi_miso:1 p1.2 ctb0.oa0.out tcpwm.line[3]:1 scb[0].uart_cts:1 scb[0].spi_clk:1 p1.3 ctb0.oa1.out tcpwm.line_compl[3]:1 scb [0].uart_rts:1 scb[0].spi_select0:1 p1.4 ctb0.oa1.inm tcpwm.line[6]:1 scb[0].spi_select1:1 p1.5 ctb0.oa1.inp tcpwm.line_compl[6]:1 scb[0].spi_select2:1 p1.6 ctb0.oa0.inp_alt tcpwm.line[7]:1 scb[0].spi_select3:1 p1.7 ctb0.oa1.inp_alt tcpwm.line_compl[7]:1 p2.0 sarmux.0 tcpwm.line[4]:1 scb[1].i2c_scl:1 sc b[1].spi_mosi:2 p2.1 sarmux.1 tcpwm.line_compl[4]:1 sc b[1].i2c_sda:1 scb[1].spi_miso:2 p2.2 sarmux.2 tcpwm.line[5]:1 scb[1].spi_clk:2 p2.3 sarmux.3 tcpwm.line_compl[5]:1 scb[1].spi_select0:2 p2.4 sarmux.4 tcpwm.line[0]:1 scb[1].spi_select1:1 p2.5 sarmux.5 tcpwm.line_compl[0]:1 scb[1].spi_select2:1 p2.6 sarmux.6 tcpwm.line[1]:1 scb[1].spi_select3:1 p2.7 sarmux.7 tcpwm.line_compl[1]:1 scb[3].spi_select0:1
document number: 001-96519 rev. *e page 12 of 41 psoc ? 4: psoc 4100m family datasheet descriptions of the power pin functions are as follows: vddd : power supply for both analog and digital sections (where there is no v dda pin). vdda : analog v dd pin where package pins allow; shorted to v ddd otherwise. vddio: i/o pin power domain. vssa: analog ground pin where package pins allow; shorted to vss otherwise vss : ground pin. vccd : regulated digital supply (1.8 v 5%). port pins can all be used as lcd commo ns, lcd segment drivers, or csd sense and shield pins can be connected to amuxbus a or b or can all be used as gpio pins that can be driven by firmware or dsi signals. p6.0 tcpwm.line[4]:0 scb[3].uart_rx:0 scb[3].i2c_scl:0 sc b[3].spi_mosi:0 p6.1 tcpwm.line_compl[4]:0 scb[3].uart_tx :0 scb[3].i2c_sda:0 scb[3].spi_miso:0 p6.2 tcpwm.line[5]:0 scb[3].uart_cts:0 scb[3].spi_clk:0 p6.3 tcpwm.line_compl[5]:0 scb[3]. uart_rts:0 scb[3].spi_select0:0 p6.4 tcpwm.line[6]:0 scb[3].spi_select1:0 p6.5 tcpwm.line_compl[6]:0 scb[3].spi_select2:0 p3.0 tcpwm.line[0]:0 scb[1].uart_rx:1 scb[1].i2c_scl:2 sc b[1].spi_mosi:0 p3.1 tcpwm.line_compl[0]:0 scb[1].uart_tx :1 scb[1].i2c_sda:2 scb[1].spi_miso:0 p3.2 tcpwm.line[1]:0 scb[1].uart_cts:1 swd_data scb[1].spi_clk:0 p3.3 tcpwm.line_compl[1]:0 scb[1].uart_ rts:1 swd_clk scb[1].spi_select0:0 p3.4 tcpwm.line[2]:0 scb[1].spi_select1:0 p3.5 tcpwm.line_compl[2]:0 scb[1].spi_select2:0 p3.6 tcpwm.line[3]:0 scb[1].spi_select3:0 p3.7 tcpwm.line_compl[3]:0 p4.0 scb[0].uart_rx:0 scb[0].i 2c_scl:1 scb[0].spi_mosi:0 p4.1 scb[0].uart_tx:0 scb[0].i 2c_sda:1 scb[0].spi_miso:0 p4.2 csd[0].c_mod scb[0].uart_cts:0 lpcomp.comp[0]:0 scb[0].spi_clk:0 p4.3 csd[0].c_sh_tank scb[0].uart_rts: 0 lpcomp.comp[1]:0 scb[0].spi_select0:0 p4.4 scb[0].spi_select1:2 p4.5 scb[0].spi_select2:2 p4.6 scb[0].spi_select3:2 p4.7 p7.0 tcpwm.line[0]:2 scb[3].uart_rx:1 scb[3].i2c_scl:1 sc b[3].spi_mosi:1 p7.1 tcpwm.line_compl[0]:2 scb[3].uart_tx :1 scb[3].i2c_sda:1 scb[3].spi_miso:1 p7.2 tcpwm.line[1]:2 scb[3].uart_cts:1 scb[3].spi_clk:1 port/pin analog alt. function 1 alt. function 2 alt. function 3 alt. function 4 alt. function 5
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 13 of 41 power the supply voltage range is 1.71 to 5.5 v with all functions and circuits operating over that range. the psoc 4100m family allows two distinct modes of power supply operation: unregulated external supply and regulated external supply modes. unregulated external supply in this mode, the psoc 4100m is powered by an external power supply that can be anywhere in the range of 1.8 to 5.5 v. this range is also designed for battery-powered operation, for instance, the chip can be powered from a battery system that starts at 3.5v and works down to 1.8 v. in this mode, the internal regulator of the psoc 4100m supplies the internal logic and the vccd output of the psoc 4100m must be bypassed to ground via an external capacitor (in the range of 1 to 1.6 f; x5r ceramic or better). the grounds, vssa and vss, must be shorted together. bypass capacitors must be used from vddd and vdda to ground, typical practice for systems in th is frequency range is to use a capacitor in the 1 f range in parallel with a smaller capacitor (0.1 f, for example). note that these are simply rules of thumb and that, for critical applic ations, the pcb layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. regulated external supply in this mode, the psoc 4100m is powered by an external power supply that must be within the range of 1.71 to 1.89 v (1.8 5%); note that this range needs to include power supply ripple. vccd and vddd pins are shorted together and bypassed. the internal regulator is disabled in firmware. power supply bypass capacitors vddd?vss and vddio-vss 0.1 f ceramic at each pin plus bulk capacitor 1 to 10 f. vdda?vssa 0.1 f ceramic at pin. additional 1 f to 10 f bulk capacitor vccd?vss 1 f ceramic capacitor at the vccd pin vref?vssa (optional) the internal bandgap may be bypassed with a 1 f to 10 f capacitor for better adc performance.
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 14 of 41 development support the psoc 4100m family has a rich set of documentation, devel- opment tools, and online resources to assist you during your development process. visit www.cypress.com/go/psoc4 to find out more. documentation a suite of documentation supports the psoc 4100m family to ensure that you can find answers to your questions quickly. this section contains a list of some of the key documents. software user guide : a step-by-step guide for using psoc creator. the software user guide shows you how the psoc creator build process works in detail, how to use source control with psoc crea tor, and much more. component datasheets : the flexibility of psoc allows the creation of new peripherals (components) long after the device has gone into production. component data sheets provide all of the information needed to select and use a particular component, including a functional description, api documentation, example code, and ac/dc specifications. application notes : psoc application notes discuss a particular application of psoc in depth; examples include brushless dc motor control and on-chip filtering. application notes often include example projects in addition to the application note document. technical reference manual : the technical reference manual (trm) contains all the technical detail you need to use a psoc device, including a comp lete description of all psoc registers. online in addition to print documentation, the cypress psoc forums connect you with fellow psoc user s and experts in psoc from around the world, 24 hours a day, 7 days a week. tools with industry standard cores, programming, and debugging interfaces, the psoc 4100m family is part of a development tool ecosystem. visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use psoc creator ide, supported third party compilers, programmers, debuggers, and development kits.
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 15 of 41 electrical specifications absolute maximum ratings device level specifications all specifications are valid for ?40 c ? ta ? 105 c and tj ? 125 c, except where noted. specific ations are valid for 1.71 v to 5.5 v, except where noted. note 1. usage above the absolute maximum conditions listed in tab l e 1 may cause permanent damage to the device. expos ure to absolute maximum conditions for extended periods of time may affect device reliabilit y. the maximum storage temperature is 150 c in compliance with jedec standard jesd2 2-a103, high temperature storage life. when used below absolute maximum conditions but a bove normal operating conditions, the device may not operate to specification. table 1. absolute maximum ratings [1] spec id# parameter description min typ max units details/conditions sid1 v dd_abs analog or digital supply relative to v ss (v ssd = v ssa ) ?0.5 ? 6 v absolute maximum sid2 v ccd_abs direct digital core voltage input relative to v ssd ?0.5 ? 1.95 v absolute maximum sid3 v gpio_abs gpio voltage; v ddd or v dda ?0.5 ? v dd +0.5 v absolute maximum sid4 i gpio_abs current per gpio ?25 ? 25 ma absolute maximum sid5 i g-pio_injection gpio injection current per pi n ?0.5 ? 0.5 ma absolute maximum bid44 esd_hbm electrostatic discharge human body model 2200 ? ? v bid45 esd_cdm electrostatic discharge charged device model 500 ? ? v bid46 lu pin current for latch-up ?140 ? 140 ma table 2. dc specifications spec id# parameter description min typ max units details / conditions sid53 v dd power supply input voltage (v dda = v ddd = v dd ) 1.8 ? 5.5 v with regulator enabled sid255 v ddd power supply input voltage unregulate d 1.71 1.8 1.89 v internally unregulated supply sid54 v ccd output voltage (for core logic) ? 1.8 ? v sid55 c efc external regulator voltage bypass 1 1.3 1.6 f x5r ceramic or better sid56 c exc power supply decoupling capacitor ? 1 ? f x5r ceramic or better active mode, v dd = 1.71 v to 5.5 v, ?40 c to +105 c sid6 i dd1 execute from flash; cpu at 6 mhz ? 2.2 2.8 ma sid7 i dd2 execute from flash; cp u at 12 mhz ? 3.7 4.2 ma sid8 i dd3 execute from flash; cp u at 24 mhz ? 6.7 7.2 ma sleep mode, ?40 c to +105 c sid21 i dd16 i 2 c wakeup, wdt, and comparators on. regulator off. ? 1.75 2.1 ma v dd = 1.71 to 1.89, 6mhz sid22 i dd17 i 2 c wakeup, wdt, and comparators on. ? 1.7 2.1 ma v dd = 1.8 to 5.5, 6 mhz sid23 i dd18 i 2 c wakeup, wdt, and comparators on. regulator off. ? 2.35 2.8 ma v dd = 1.71 to 1.89, 12 mhz sid24 i dd19 i 2 c wakeup, wdt, and comparators on. ? 2.25 2.8 ma v dd = 1.8 to 5.5, 12 mhz
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 16 of 41 deep sleep mode, ?40 c to + 60 c sid30 i dd25 i 2 c wakeup and wdt on. regulator off. ? 1.55 20 a v dd = 1.71 to 1.89 sid31 i dd26 i 2 c wakeup and wdt on. ? 1.35 15 a v dd = 1.8 to 3.6 sid32 i dd27 i 2 c wakeup and wdt on. ? 1.5 15 a v dd = 3.6 to 5.5 deep sleep mode, +85 c sid33 i dd28 i 2 c wakeup and wdt on. regulator off. ? ? 60 a v dd = 1.71 to 1.89 sid34 i dd29 i 2 c wakeup and wdt on. ? ? 45 a v dd = 1.8 to 3.6 sid35 i dd30 i 2 c wakeup and wdt on. ? ? 30 a v dd = 3.6 to 5.5 deep sleep mode, +105 c sid33q i dd28q i 2 c wakeup and wdt on. regulator off. ? ? 135 a v dd = 1.71 to 1.89 sid34q i dd29q i 2 c wakeup and wdt on. ? ? 180 a v dd = 1.8 to 3.6 sid35q i dd30q i 2 c wakeup and wdt on. ? ? 140 a v dd = 3.6 to 5.5 hibernate mode, ?40 c to + 60 c sid39 i dd34 regulator off. ? 150 3000 na v dd = 1.71 to 1.89 sid40 i dd35 ? 150 1000 na v dd = 1.8 to 3.6 sid41 i dd36 ? 150 1100 na v dd = 3.6 to 5.5 hibernate mode, +85 c sid42 i dd37 regulator off. ? ? 4500 na v dd = 1.71 to 1.89 sid43 i dd38 ? ? 3500 na v dd = 1.8 to 3.6 sid44 i dd39 ? ? 3500 na v dd = 3.6 to 5.5 hibernate mode, +105 c sid42q i dd37q regulator off. ? ? 19.4 a v dd = 1.71 to 1.89 sid43q i dd38q ??17av dd = 1.8 to 3.6 sid44q i dd39q ??16av dd = 3.6 to 5.5 stop mode, +85 c sid304 i dd43a stop mode current; v dd = 3.6 v ? 35 85 na t = ?40 c to +60 c sid304a i dd43b stop mode current; v dd = 3.6 v ? ? 1450 na t = +85 c stop mode, +105 c sid304q i dd43aq stop mode current; v dd = 3.6 v ? ? 5645 na xres current sid307 i dd_xr supply current while xres asserted ? 2 5 ma table 2. dc specifications (continued) spec id# parameter description min typ max units details / conditions
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 17 of 41 gpio table 3. ac specifications spec id# parameter description min typ max units details/ conditions sid48 f cpu cpu frequency dc ? 24 mhz 1.71 ?? v dd ?? 5.5 sid49 t sleep wakeup from sleep mode ? 0 ? s guaranteed by characterization sid50 t deepsleep wakeup from deep sleep mode ? ? 25 s 24 mhz imo. guaranteed by characterization sid51 t hibernate wakeup from hibernate mode ? ? 0.7 ms guaranteed by characterization sid51a t stop wakeup from stop mode ? ? 2 ms guaranteed by characterization sid52 t resetwidth external reset pulse width 1 ? ? s guaranteed by characterization note 2. v ih must not exceed v ddd + 0.2 v. table 4. gpio dc specifications spec id# parameter description min typ max units details/ conditions sid57 v ih [2] input voltage high threshold 0.7 v ddd ?? vcmos input sid57a iihs input current when pad > v ddio for ovt inputs ? ? 10 a per i 2 c spec sid58 v il input voltage low threshold ? ? 0.3 v ddd vcmos input sid241 v ih [2] lvttl input, v ddd < 2.7 v 0.7 v ddd ?? v sid242 v il lvttl input, v ddd < 2.7 v ? ? 0.3 v ddd v sid243 v ih [2] lvttl input, v ddd ? 2.7 v 2.0 ? ? v sid244 v il lvttl input, v ddd ? 2.7 v ? ? 0.8 v sid59 v oh output voltage high level v ddd ?0.6 ?? vi oh = 4 ma at 3v v ddd sid60 v oh output voltage high level v ddd ?0.5 ?? vi oh = 1 ma at 1.8 v v ddd sid61 v ol output voltage low level ? ? 0.6 v i ol = 4 ma at 1.8 v v ddd sid62 v ol output voltage low level ? ? 0.6 v i ol = 8ma at 3v v ddd sid62a v ol output voltage low level ? ? 0.4 v i ol = 3ma at 3v v ddd sid63 r pullup pull-up resistor 3.5 5.6 8.5 k ? sid64 r pulldown pull-down resistor 3.5 5.6 8.5 k ? sid65 i il input leakage current (absolute value) ? ? 2 na 25 c, v ddd = 3.0 v. guaranteed by characterization
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 18 of 41 sid65a i il_ctbm input leakage current (absolute value) for ctbm pins ? ? 4 na guaranteed by characterization sid66 c in input capacitance ? ? 7 pf sid67 v hysttl input hysteresis lvttl 25 40 ? mv v ddd ? 2.7 v sid68 v hyscmos input hysteresis cmos 0.05 v ddd ??mv sid69 i diode current through protection diode to v dd /vss ??100 a guaranteed by characterization sid69a i tot_gpio maximum total source or sink chip current ? ? 200 ma guaranteed by characterization table 4. gpio dc specifications (continued) spec id# parameter description min typ max units details/ conditions note 3. simultaneous switching transitions on many fully-loaded gpio pi ns may cause ground perturbations depending on several factors including pcb and decoupling capacitor design. for applications that are very sensitive to gr ound perturbations, the slower gpio slew rate setting may be us ed. table 5. gpio ac specifications (guaranteed by characterization) [3] spec id# parameter description min typ max units details/ conditions sid70 t risef rise time in fast strong mode 2 ? 12 ns 3.3 v v ddd , cload = 25 pf sid71 t fallf fall time in fast strong mode 2 ? 12 ns 3.3 v v ddd , cload = 25 pf sid72 t rises rise time in slow strong mode 10 ? 60 ns 3.3 v v ddd , cload = 25 pf sid73 t falls fall time in slow strong mode 10 ? 60 ns 3.3 v v ddd , cload = 25 pf sid74 f gpiout1 gpio fout;3.3 v ? v ddd ?? 5.5 v. fast strong mode. ? ? 24 mhz 90/10%, 25 pf load, 60/40 duty cycle sid75 f gpiout2 gpio fout;1.7 v ?? v ddd ?? 3.3 v. fast strong mode. ? ? 16.7 mhz 90/10%, 25 pf load, 60/40 duty cycle sid76 f gpiout3 gpio fout;3.3 v ?? v ddd ?? 5.5 v. slow strong mode. ? ? 7 mhz 90/10%, 25 pf load, 60/40 duty cycle sid245 f gpiout4 gpio fout;1.7 v ?? v ddd ?? 3.3 v. slow strong mode. ? ? 3.5 mhz 90/10%, 25 pf load, 60/40 duty cycle sid246 f gpioin gpio input operating frequency; 1.71 v ?? v ddd ?? 5.5 v ? ? 48 mhz 90/10% v io
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 19 of 41 xres table 6. xres dc specifications spec id# parameter description min typ max units details/ conditions sid77 v ih input voltage high threshold 0.7 v ddd ? ? v cmos input sid78 v il input voltage low threshold ? ? 0.3 v ddd v cmos input sid79 r pullup pull-up resistor 3.5 5.6 8.5 k ? sid80 c in input capacitance ? 3 ? pf sid81 v hysxres input voltage hysteresis ? 100 ? mv guaranteed by characterization sid82 i diode current through protection diode to v ddd /v ss ? ? 100 a guaranteed by characterization table 7. xres ac specifications spec id# parameter description min typ max units details/ conditions sid83 t resetwidth reset pulse width 1 ? ? s guaranteed by characterization
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 20 of 41 analog peripherals opamp table 8. opamp specifications (guaranteed by characterization) spec id# parameter description min typ max units details/ conditions i dd opamp block current. no load. ? ? ? ? sid269 i dd_hi power = high ? 1100 1850 a sid270 i dd_med power = medium ? 550 950 a sid271 i dd_low power = low ? 150 350 a gbw load = 20 pf, 0.1 ma. v dda = 2.7 v ? ? ? ? sid272 gbw_hi power = high 6 ? ? mhz sid273 gbw_med power = medium 4 ? ? mhz sid274 gbw_lo power = low ? 1 ? mhz i out_max v dda ? 2.7 v, 500 mv from rail ? ? ? ? sid275 i out_max_hi power = high 10 ? ? ma sid276 i out_max_mid power = medium 10 ? ? ma sid277 i out_max_lo power = low ? 5 ? ma i out v dda = 1.71 v, 500 mv from rail ? ? ? ? sid278 i out_max_hi power = high 4 ? ? ma sid279 i out_max_mid power = medium 4 ? ? ma sid280 i out_max_lo power = low ? 2 ? ma sid281 v in input voltage range ?0.05 ? vdda ? 0.2 v charge-pump on, v dda ?? 2.7 v sid282 v cm input common mode voltage ?0.05 ? vdda ? 0.2 v charge-pump on, v dda ?? 2.7 v v out v dda ? 2.7 v ? ? ? sid283 v out_1 power = high, iload=10 ma 0.5 ? vdda ? 0.5 v sid284 v out_2 power = high, iload=1 ma 0.2 ? vdda ? 0.2 v sid285 v out_3 power = medium, iload=1 ma 0.2 ? vdda ? 0.2 v sid286 v out_4 power = low, iload=0.1 ma 0.2 ? vdda ? 0.2 v sid288 v os_tr offset voltage, trimmed 1 0.5 1 mv high mode sid288a v os_tr offset voltage, trimmed ? 1 ? mv medium mode sid288b v os_tr offset voltage, trimmed ? 2 ? mv low mode sid290 v os_dr_tr offset voltage drift, trimmed ?10 3 10 v/c high mode. t a 85 c. sid290q v os_dr_tr offset voltage drift, trimmed 15 3 15 v/c high mode. t a 105 c sid290a v os_dr_tr offset voltage drift, trimmed ? 10 ? v/c medium mode sid290b v os_dr_tr offset voltage drift, trimmed ? 10 ? v/c low mode sid291 cmrr dc common mode rejection ratio. high-power mode. common model voltage range from 0.5 v to vdda - 0.5 v. 60 70 ? db v ddd = 3.6 v sid292 psrr at 1 khz, 100-mv ripple 70 85 ? db v ddd = 3.6 v noise ? ? ? ?
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 21 of 41 sid293 v n1 input referred, 1 hz - 1ghz, power = high ? 94 ? vrms sid294 v n2 input referred, 1 khz, power = high ? 72 ? nv/rthz sid295 v n3 input referred, 10khz, power = high ? 28 ? nv/rthz sid296 v n4 input referred, 100khz, power = high ? 15 ? nv/rthz sid297 cload stable up to maximum load. perfor- mance specs at 50 pf. ??125pf sid298 slew_rate cload = 50 pf, power = high, v dda ? 2.7 v 6??v/s sid299 t_op_wake from disable to enable, no external rc dominating ?25?s sid299a ol_gain open loop gain ? 90 ? db comp_mode comparator mode; 50 mv drive, trise = tfall (approx.) ??? sid300 t pd1 response time; power = high ? 150 ? ns sid301 t pd2 response time; power = medium ? 400 ? ns sid302 t pd3 response time; power = low ? 2000 ? ns sid303 vhyst_op hysteresis ? 10 ? mv deep sleep mode mode 2 is lowest current range. mode 1 has higher gbw. deep sleep mode. v dda ? 2.7 v. sid_ds_1 idd_hi_m1 mode 1, high current ? 1400 ? ua 25 c sid_ds_2 idd_med_m1 mode 1, medium current ? 700 ? ua 25 c sid_ds_3 idd_low_m1 mode 1, low current ? 200 ? ua 25 c sid_ds_4 idd_hi_m2 mode 2, high current ? 120 ? ua 25 c sid_ds_5 idd_med_m2 mode 2, medium current ? 60 ? ua 25 c sid_ds_6 idd_low_m2 mode 2, low current ? 15 ? ua 25 c sid_ds_7 gbw_hi_m1 mode 1, high current ? 4 ? mhz 25 c sid_ds_8 gbw_med_m1 mode 1, medium current ? 2 ? mhz 25 c sid_ds_9 gbw_low_m1 mode 1, low current ? 0.5 ? mhz 25 c sid_ds_10 gbw_hi_m2 mode 2, high current ? 0.5 ? mhz 20-pf load, no dc load 0.2 v to v dda -1.5 v sid_ds_11 gbw_med_m2 mode 2, medium current ? 0.2 ? mhz 20-pf load, no dc load 0.2 v to v dda -1.5 v sid_ds_12 gbw_low_m2 mode 2, low current ? 0.1 ? mhz 20-pf load, no dc load 0.2 v to v dda -1.5 v sid_ds_13 vos_hi_m1 mode 1, high curren t ? 5 ? mv with trim 25 c, 0.2 v to v dda -1.5 v sid_ds_14 vos_med_m1 mode 1, medium current ? 5 ? mv with trim 25 c, 0.2 v to v dda -1.5 v sid_ds_15 vos_low_m1 mode 1, low curre nt ? 5 ? mv with trim 25 c, 0.2 v to v dda -1.5 v sid_ds_16 vos_hi_m2 mode 2, high curren t ? 5 ? mv with trim 25 c, 0.2 v to v dda -1.5 v sid_ds_17 vos_med_m2 mode 2, medium current ? 5 ? mv with trim 25 c, 0.2 v to v dda -1.5 v table 8. opamp specifications (guaranteed by characterization) (continued) spec id# parameter description min typ max units details/ conditions
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 22 of 41 comparator sid_ds_18 vos_low_m2 mode 2, low curre nt ? 5 ? mv with trim 25 c, 0.2 v to v dda -1.5 v sid_ds_19 iout_hi_m1 mode 1, high current ? 10 ? ma output is 0.5 v to vdda-0.5 v sid_ds_20 iout_med_m1 mode 1, medium current ? 10 ? ma output is 0.5 v to vdda-0.5 v sid_ds_21 iout_low_m1 mode 1, low current ? 4 ? ma output is 0.5 v to vdda-0.5 v sid_ds_22 iout_hi_m2 mode 2, high current ? 1 ? ma output is 0.5 v to v dda -0.5 v sid_ds_23 iout_med_m2 mode 2, medium current ? 1 ? ma output is 0.5 v to v dda -0.5 v sid_ds_24 iout_low_m2 mode 2, low current ? 0.5 ? ma output is 0.5 v to v dda -0.5 v table 8. opamp specifications (guaranteed by characterization) (continued) spec id# parameter description min typ max units details/ conditions table 9. comparator dc specifications spec id# parameter description min typ max units details/ conditions sid85 v offset2 input offset voltage, common mode voltage range from 0 to v dd -1 ?? 4 mv sid85a v offset3 input offset voltage. ultra low-power mode (v ddd 2.2v for temp < 0c, v ddd 1.8 v for temp > 0 c). ? 12 ? mv sid86 v hyst hysteresis when enabled, common mode voltage range from 0 to v dd -1. ? 10 35 mv guaranteed by charac- terization sid87 v icm1 input common mode voltage in normal mode 0?v ddd ? 0.1 v modes 1 and 2. sid247 v icm2 input common mode voltage in low power mode 0?v ddd v sid247a v icm3 input common mode voltage in ultra low power mode (v ddd 2.2 v for te m p < 0 c , v ddd 1.8 v for temp > 0 c) 0?v ddd ? 1.15 v sid88 cmrr common mode rejection ratio 50 ? ? db v ddd ? 2.7 v. guaranteed by charac- terization sid88a cmrr common mode rejection ratio 42 ? ? db v ddd ? 2.7 v. guaranteed by charac- terization sid89 i cmp1 block current, normal mode ? ? 400 a guaranteed by charac- terization sid248 i cmp2 block current, low power mode ? ? 100 a guaranteed by charac- terization sid259 i cmp3 block current, ultra low power mode (v ddd 2.2v for temp < 0c, v ddd 1.8 v for temp > 0 c) ? 6 28 a guaranteed by charac- terization sid90 z cmp dc input impedance of comparator 35 ? ? m ? guaranteed by charac- terization
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 23 of 41 temperature sensor sar adc table 10. comparator ac specifications (guaranteed by characterization) spec id# parameter description min typ max units details/conditions sid91 t resp1 response time, normal mode ? ? 110 ns 50-mv overdrive sid258 t resp2 response time, low power mode ? ? 200 ns 50-mv overdrive sid92 t resp3 response time, ultra low power mode (v ddd 2.2 v for temp < 0 c, v ddd 1.8v for temp > 0c) ? ? 15 s 200-mv overdrive table 11. temperature sensor specifications spec id# parameter description min typ max units details/conditions sid93 t sensacc temperature sensor accuracy ?5 1 +5 c ?40 to +85 c table 12. sar adc dc specifications spec id# parameter description min typ max units details/conditions sid94 a_res resolution ? ? 12 bits sid95 a_chnis_s number of channels - single ended ? ? 16 8 full speed sid96 a-chnks_d number of channels - differential ? ? 8 diff inputs use neighboring i/o sid97 a-mono monotonicity ? ? ? yes. based on characterization sid98 a_gainerr gain error ? ? 0.1 % with external reference. sid99 a_offset input offset voltage ? ? 2 mv measured with 1-v v ref. sid100 a_isar current consumption ? ? 1 ma sid101 a_vins input voltage range - single ended v ss ?v dda v based on device characterization sid102 a_vind input voltage range - differential v ss ? v dda v based on device characterization sid103 a_inres input resistance ? ? 2.2 k ? based on device characterization sid104 a_incap input capacitance ? ? 10 pf based on device characterization table 13. sar adc ac specifications (guaranteed by characterization) spec id# parameter description min typ max units details/conditions sid106 a_psrr power supply rejection ratio 70 ? ? db sid107 a_cmrr common mode rejection ratio 66 ? ? db measured at 1 v sid108 a_samp_1 sample rate with external reference bypass cap ? ? 806 ksps
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 24 of 41 csd sid108a a_samp_2 sample rate with no bypass cap. reference = v dd ? ? 500 ksps sid108b a_samp_3 sample rate with no bypass cap. internal reference ? ? 100 ksps sid109 a_sndr signal-to-noise and distortion ratio (sinad) 66 ? ? db f in = 10 khz sid111 a_inl integral non linearity ?1.4 ? +1.4 lsb v dd = 1.71 to 5.5, 806 ksps, vref = 1 to 5.5. sid111a a_inl integral non linearity ?1.4 ? +1.4 lsb v ddd = 1.71 to 3.6, 806 ksps, vref = 1.71 to v ddd . sid111b a_inl integral non linearity ?1.4 ? +1.4 lsb v ddd = 1.71 to 5.5, 500 ksps, vref = 1 to 5.5. sid112 a_dnl differential non linearity ?0.9 ? +1.35 lsb v ddd = 1.71 to 5.5, 806 ksps, vref = 1 to 5.5. sid112a a_dnl differential non linearity ?0.9 ? +1.35 lsb v ddd = 1.71 to 3.6, 806 ksps, vref = 1.71 to v ddd . sid112b a_dnl differential non linearity ?0.9 ? +1.35 lsb v ddd = 1.71 to 5.5, 500 ksps, vref = 1 to 5.5. sid113 a_thd total harmonic distortion ? ? ?65 db f in = 10 khz. table 13. sar adc ac specifications (guaranteed by characterization) (continued) spec id# parameter description min typ max units details/conditions table 14. csd block specification spec id# parameter description min typ max units details/ conditions csd specification sid308 vcsd voltage range of operation 1.71 ? 5.5 v sid309 idac1 dnl for 8-bit resolution ?1 ? 1 lsb sid310 idac1 inl for 8-bit resolution ?3 ? 3 lsb sid311 idac2 dnl for 7-bit resolution ?1 ? 1 lsb sid312 idac2 inl for 7-bit resolution ?3 ? 3 lsb sid313 snr ratio of counts of finger to noise. guaranteed by characterization 5? ?ratio capacitance range of 9 to 35 pf, 0.1 pf sensitivity sid314 idac1_crt1 output current of idac1 (8-bits) in high range ? 612 ? a sid314a idac1_crt2 output curren t of idac1(8-bits) in low range ? 306 ? a sid315 idac2_crt1 output current of idac2 (7-bits) in high range ?304.8 ? a sid315a idac2_crt2 output current of idac2 (7-bits) in low range ?152.4 ? a
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 25 of 41 digital peripherals the following specifications apply to the timer/counter/pwm peripheral in timer mode. timer/counter/pwm i 2 c table 15. tcpwm specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid.tcpwm.1 itcpwm1 block current consumption at 3 mhz ? ? 45 a all modes (timer/counter/pwm) sid.tcpwm.2 itcpwm2 block current consumption at 12 mhz ? ? 155 a all modes (timer/counter/pwm) sid.tcpwm.2a itcpwm3 block current consumption at 48 mhz ? ? 650 a all modes (timer/counter/pwm) sid.tcpwm.3 tcpwmfreq operating frequency ? ? fc mhz fc max = fcpu. maximum = 24 mhz sid.tcpwm.4 tpwmenext input trigger pulse width for all trigger events 2/fc ? ? ns trigger events can be stop, start, reload, count, capture, or kill depending on which mode of operation is selected. sid.tcpwm.5 tpwmext output tr igger pulse widths 2/fc ? ? ns minimum possible width of overflow, underflow, and cc (counter equals compare value) trigger outputs sid.tcpwm.5a tcres resolution of counter 1/fc ? ? ns minimum time between successive counts sid.tcpwm.5b pwmres pw m resolution 1/fc ? ? ns minimum pulse width of pwm output sid.tcpwm.5c qres qu adrature inputs resolution 1/fc ? ? ns minimum pulse width between quadrature phase inputs. table 16. fixed i 2 c dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid149 i i2c1 block current consumption at 100 khz ? ? 50 a sid150 i i2c2 block current consumption at 400 khz ? ? 135 a sid151 i i2c3 block current consumption at 1 mbps ? ? 310 a sid152 i i2c4 i 2 c enabled in deep sleep mode ? ? 1.4 a table 17. fixed i 2 c ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid153 f i2c1 bit rate ? ? 1 mbps
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 26 of 41 lcd direct drive spi specifications table 18. lcd direct drive dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid154 i lcdlow operating current in low power mode ? 5 ? a 16 4 small segment disp. at 50 hz sid155 c lcdcap lcd capacitance per segment/common driver ? 500 5000 pf guaranteed by design sid156 lcd offset long-term segment offset ? 20 ? mv sid157 i lcdop1 pwm mode current. 5-v bias. 24-mhz imo ? 0.6 ? ma 32 4 segments. 50 hz, 25 c sid158 i lcdop2 pwm mode current. 3.3-v bias. 24-mhz imo. ? 0.5 ? ma 32 4 segments. 50 hz, 25 c table 19. lcd direct drive ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid159 f lcd lcd frame rate 10 50 150 hz table 20. fixed uart dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid160 i uart1 block current consumption at 100 kbits/sec ??55 a sid161 i uart2 block current consumption at 1000 kbits/sec ? ? 312 a table 21. fixed uart ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid162 f uart bit rate ? ? 1 mbps table 22. fixed spi dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid163 i spi1 block current consumption at 1 mbits/sec ? ? 360 a sid164 i spi2 block current consumption at 4 mbits/sec ? ? 560 a sid165 i spi3 block current consumption at 8 mbits/sec ? ? 600 a table 23. fixed spi ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid166 f spi spi operating frequency (master; 6x oversampling) ?? 8mhz
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 27 of 41 memory table 24. fixed spi master mode ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid167 t dmo mosi valid after sclock driving edge ? ? 15 ns sid168 t dsi miso valid before sc lock capturing edge. full clock, late miso sampling used 20 ? ? ns sid169 t hmo previous mosi data hold time with respect to capturing edge at slave 0??ns table 25. fixed spi slave mode ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid170 t dmi mosi valid before sclock capturing edge 40 ? ? ns sid171 t dso miso valid after sclock driving edge ? ? 42 + 3 (1/fcpu) ns sid171a t dso_ext miso valid after sclock driving edge in ext. clock mode ? ? 48 ns sid172 t hso previous miso data hold time 0 ? ? ns sid172a t sselsck ssel valid to first sck valid edge 100 ? ? ns table 26. flash dc specifications spec id parameter description min typ max units details/conditions sid173 v pe erase and program voltage 1.71 ? 5.5 v table 27. flash ac specifications spec id parameter description min typ max units details/conditions sid174 t rowwrite row (block) write time (erase and program) ? ? 20 ms row (block) = 128 bytes sid175 t rowerase row erase time ? ? 13 ms sid176 t rowprogram row program time after erase ? ? 7 ms sid178 t bulkerase bulk erase time (128 kb) ? ? 35 ms sid179 t sectorerase sector erase time (8 kb) ? ? 15 ms sid180 t devprog total device program time ? ? 15 seconds guaranteed by characterization sid181 f end flash endurance 100 k ? ? cycles guaranteed by characterization sid182 f ret flash retention. t a ? 55 c, 100 k p/e cycles 20 ? ? years guaranteed by characterization sid182a flash retention. t a ? 85 c, 10 k p/e cycles 10 ? ? years guaranteed by characterization sid182b f retq flash retention. t a ? 105 c, 10k p/e cycles, ? three years at t a 85 c 10 20 ? years guaranteed by characterization.
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 28 of 41 system resources power-on-reset (por) with brown out voltage monitors table 28. imprecise power on reset (pres) spec id parameter description min typ max units details/conditions sid185 v riseipor rising trip voltage 0.80 ? 1.45 v guaranteed by charac- terization sid186 v fallipor falling trip voltage 0.75 ? 1.4 v guaranteed by charac- terization sid187 v iporhyst hysteresis 15 ? 200 mv guaranteed by charac- terization table 29. precise power on reset (por) spec id parameter description min typ max units details/conditions sid190 v fallppor bod trip voltage in active and sleep modes 1.64 ? ? v guaranteed by charac- terization sid192 v falldpslp bod trip voltage in deep sleep 1.4 ? ? v guaranteed by charac- terization table 30. voltage monitors dc specifications spec id parameter description min typ max units details/conditions sid195 v lvi1 lvi_a/d_sel[3:0] = 0000b 1.71 1.75 1.79 v sid196 v lvi2 lvi_a/d_sel[3:0] = 0001b 1.76 1.80 1.85 v sid197 v lvi3 lvi_a/d_sel[3:0] = 0010b 1.85 1.90 1.95 v sid198 v lvi4 lvi_a/d_sel[3:0] = 0011b 1.95 2.00 2.05 v sid199 v lvi5 lvi_a/d_sel[3:0] = 0100b 2.05 2.10 2.15 v sid200 v lvi6 lvi_a/d_sel[3:0] = 0101b 2.15 2.20 2.26 v sid201 v lvi7 lvi_a/d_sel[3:0] = 0110b 2.24 2.30 2.36 v sid202 v lvi8 lvi_a/d_sel[3:0] = 0111b 2.34 2.40 2.46 v sid203 v lvi9 lvi_a/d_sel[3:0] = 1000b 2.44 2.50 2.56 v sid204 v lvi10 lvi_a/d_sel[3:0] = 1001b 2.54 2.60 2.67 v sid205 v lvi11 lvi_a/d_sel[3:0] = 1010b 2.63 2.70 2.77 v sid206 v lvi12 lvi_a/d_sel[3:0] = 1011b 2.73 2.80 2.87 v sid207 v lvi13 lvi_a/d_sel[3:0] = 1100b 2.83 2.90 2.97 v sid208 v lvi14 lvi_a/d_sel[3:0] = 1101b 2.93 3.00 3.08 v sid209 v lvi15 lvi_a/d_sel[3:0] = 1110b 3.12 3.20 3.28 v sid210 v lvi16 lvi_a/d_sel[3:0] = 1111b 4.39 4.50 4.61 v sid211 lvi_idd block current ? ? 100 a guaranteed by charac- terization table 31. voltage monitors ac specifications spec id parameter description min typ max units details/conditions sid212 t montrip voltage monitor trip time ? ? 1 s guaranteed by character- ization
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 29 of 41 swd interface internal main oscillator internal low-speed oscillator table 32. swd interface specifications spec id parameter description min typ max units details/conditions sid213 f_swdclk1 3.3 v ? v dd ? 5.5 v ? ? 14 mhz swdclk 1/3 cpu clock frequency sid214 f_swdclk2 1.71 v ? v dd ? 3.3 v ? ? 7 mhz swdclk 1/3 cpu clock frequency sid215 t_swdi_setup t = 1/f swdclk 0.25*t ? ? ns guaranteed by characterization sid216 t_swdi_hold t = 1/f swdclk 0.25*t ? ? ns guaranteed by characterization sid217 t_swdo_valid t = 1/f swdclk ? ? 0.5*t ns guaranteed by characterization sid217a t_swdo_hold t = 1/f swdclk 1 ? ? ns guaranteed by characterization table 33. imo dc specifications (guaranteed by design) spec id parameter description min typ max units details/conditions sid218 i imo1 imo operating current at 48 mhz ? ? 1000 a sid219 i imo2 imo operating current at 24 mhz ? ? 325 a sid220 i imo3 imo operating current at 12 mhz ? ? 225 a sid221 i imo4 imo operating current at 6 mhz ? ? 180 a sid222 i imo5 imo operating current at 3 mhz ? ? 150 a table 34. imo ac specifications spec id parameter description min typ max units details/conditions sid223 f imotol1 frequency variation from 3 to 48 mhz ? ? 2 % 3% if t a > 85 c and imo frequency < 24 mhz sid226 t startimo imo startup time ? ? 12 s sid227 t jitrmsimo1 rms jitter at 3 mhz ? 156 ? ps sid228 t jitrmsimo2 rms jitter at 24 mhz ? 145 ? ps sid229 t jitrmsimo3 rms jitter at 48 mhz ? 139 ? ps table 35. ilo dc specifications (guaranteed by design) spec id parameter description min typ max units details/conditions sid231 i ilo1 ilo operating current at 32 khz ? 0.3 1.05 a guaranteed by characterization sid233 i iloleak ilo leakage current ? 2 15 na guaranteed by design
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 30 of 41 table 36. ilo ac specifications spec id parameter description min typ max units details/conditions sid234 t startilo1 ilo startup time ? ? 2 ms guaranteed by character- ization sid236 t iloduty ilo duty cycle 40 50 60 % guaranteed by character- ization sid237 f ilotrim1 32 khz trimmed frequency 15 32 50 khz max ilo frequency is 70 khz if t a > 85 c table 37. external clock specifications spec id parameter description min typ max units details/conditions sid305 extclkfreq external clock input frequency 0 ? 48 mhz guaranteed by character- ization sid306 extclkduty duty cycle; measured at v dd/2 45 ? 55 % guaranteed by character- ization table 38. watch crystal oscillator (wco) specifications spec id parameter description min typ max units details / conditions imo wco-pll calibrated mode sid330 imo wco1 frequency variation with imo set to 3mhz ?0.6 ? 0.6 % does not include wco tolerance sid331 imo wco2 frequency variation with imo set to 5mhz ?0.4 ? 0.4 % does not include wco tolerance sid332 imo wco3 frequency variation with imo set to 7mhz or 9mhz ?0.3 ? 0.3 % does not include wco tolerance sid333 imo wco4 all other imo frequency settings ?0.2 ? 0.2 % does not include wco tolerance wco specifications sid398 f wco crystal frequency ? 32.768 khz sid399 f tol frequency tolerance ? 50 250 ppm with 20-ppm crystal. sid400 esr equivalent series resistance ? 50 ? k ? sid401 pd drive level ? ? 1 w sid402 t start startup time ? ? 500 ms sid403 c l crystal load capacitance 6 ? 12.5 pf sid404 c 0 crystal shunt capacitance ? 1.35 ? pf sid405 i wco1 operating current (high power mode) ? ? 8 ua table 39. block specs spec id parameter description min typ max units details/conditions sid257 t ws24 * number of wait states at 24 mhz 1 ? ? cpu execution from flash sid260 v refsar trimmed internal reference to sar ?1 ? +1 % percentage of vbg (1.024 v). guaranteed by character- ization sid261 f sarintref sar operating speed without external reference bypass ? ? 100 ksps 12-bit resolution. guaranteed by characterization sid262 t clkswitch clock switching from clk1 to clk2 in clk1 periods 3 ? 4 periods guaranteed by design * t ws24 is guaranteed by design
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 31 of 41 ordering information the psoc 4100m family part numbers and fe atures are listed in the following table. category mpn features package max cpu speed (mhz) flash (kb) sram (kb) udb opamp (ctbm) csd idac (1x7-bit, 1-8-bit) direct lcd drive 12-bit sar adc lp comparators tcpwm blocks scb blocks can gpio 44-tqfp 48-tqfp 64-tqfp (0.5-mm pitch) 64-tqfp (0.8-mm pitch) 68-qfn 4125 cy8c4125azi-m433 24 32 4 0 2 ? ? ? 806 ksps 2 8 4 ? 38 ? ? ??? cy8c4125azi-m443 24 32 4 0 2 ? ? ? 806 ksps 2 8 4 ? 38 ? ? ??? cy8c4125azi-m445 24 32 4 0 2 ? ? ? 806 ksps 2 8 4 ? 51 ? ? ? ?? CY8C4125LTI-M445 24 32 4 0 2 ? ? ? 806 ksps 2 8 4 ? 55 ? ? ? ? ? cy8c4125axi-m445 24 32 4 0 2 ? ? ? 806 ksps 2 8 4 ? 51 ? ? ? ? ? 4126 cy8c4126azi-m443 24 64 8 0 2 ? ? ? 806 ksps 2 8 4 ? 38 ? ? ??? cy8c4126axi-m443 24 64 8 0 2 ? ? ? 806 ksps 2 8 4 ? 36 ? ???? cy8c4126azi-m445 24 64 8 0 2 ? ? ? 806 ksps 2 8 4 ? 51 ? ? ? ?? cy8c4126azi-m475 24 64 8 0 4 ? ? ? 806 ksps 2 8 4 ? 51 ? ? ? ?? cy8c4126lti-m445 24 64 8 0 2 ? ? ? 806 ksps 2 8 4 ? 55 ? ? ? ? ? cy8c4126lti-m475 24 64 8 0 4 ? ? ? 806 ksps 2 8 4 ? 55 ? ? ? ? ? cy8c4126axi-m445 24 64 8 0 2 ? ? ? 806 ksps 2 8 4 ? 51 ? ? ? ? ? 4127 cy8c4127lti-m475 24 128 16 0 4 ?? ? 806 ksps 2 8 4 ? 55 ? ? ? ? ? cy8c4127azi-m475 24 128 16 0 4 ? ? ? 806 ksps 2 8 4 ? 51 ? ? ? ?? cy8c4127azi-m485 24 128 16 0 4 ??? 806 ksps 2 8 4 ? 51 ? ? ? ?? cy8c4127axi-m485 24 128 16 0 4 ??? 806 ksps 2 8 4 ? 51 ? ? ? ? ?
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 32 of 41 the nomenclature used in the preceding table is based on the following part numbering convention: part numbering conventions the part number fields are defined as follows. field description values meaning cy8c cypress prefix 4 architecture 4 psoc 4 a family 1 4100 family b cpu speed 4 48 mhz c flash capacity 416 kb 532 kb 664 kb 7 128 kb de package code ax, az tqfp lq qfn bu bga fd csp f temperature range i industrial q extended industrial s silicon family n/a psoc 4 base series l psoc 4 l-series bl psoc 4 ble m psoc 4 m-series xyz attributes code 000-999 code of fe ature set in the specific family architecture cypress prefix family group within architecture speed grade flash capacity package code temperature range attributes code cy8c 4 a e d c bfx s -y z silicon family
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 33 of 41 packaging the description of the psoc4100m package dimensions follows. spec id# package description package dwg # pkg_1 68-pin qfn 68 qfn, 8 mm x 8 mm x 1.0 mm height with 0.4 mm pitch 001-09618 pkg_2 64-pin tqfp 64 tqfp , 10 mm x10 mm x 1.4 mm height with 0.5 mm pitch 51-85051 pkg_4 64-pin tqfp 64 tqfp , 14 mm x14 mm x 1.4 mm height with 0.8 mm pitch 51-85046 pkg_5 48-pin tqfp 48 tqfp, 7 mm x 7 mm x 1.4 mm height with 0.5 mm pitch 51-85135 pkg_6 44-pin tqfp 44 tqfp, 10 mm x 10 mm x 1.4 mm height with 0.8 mm pitch 51-85064 table 40. package characteristics parameter description conditions min typ max units t a operating ambient temperature ?40 25 85 c t j operating junction temperature ?40 ? 100 c t ja package ja (68-pin qfn) ? 16.8 ? c/watt t jc package jc (68-pin qfn) ? 2.9 ? c/watt t ja package ja (64-pin tqfp, 0.5-mm pitch) ? 56 ? c/watt t jc package jc (64-pin tqfp, 0.5-mm pitch) ? 19.5 ? c/watt t ja package ja (64-pin tqfp, 0.8-mm pitch) ? 66.4 ? c/watt t jc package jc (64-pin tqfp, 0.8-mm pitch) ? 18.2 ? c/watt t ja package ja (48-pin tqfp, 0.5-mm pitch) ? 67.3 ? c/watt t jc package jc (48-pin tqfp, 0.5-mm pitch) ? 30.4 ? c/watt t ja package ja (44-pin tqfp, 0.8-mm pitch) ? 57 ? c/watt t jc package jc (44-pin tqfp, 0.8-mm pitch) ? 25.9 ? c/watt table 41. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature all packages 260 c 30 seconds table 42. package moisture sensitivity level (msl), ipc/jedec j-std-2 package msl all packages msl 3
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 34 of 41 figure 5. 68-pin 8 8 1.0 mm qfn package outline figure 6. 64-pin 10 10 1.4 mm tqfp package outline 001-09618 *e 51-85051 *d
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 35 of 41 figure 7. 64-pin 14 14 1.4 mm tqfp package outline figure 8. 48-pin 7 7 1.4 mm tqfp package outline 51-85046 *g 51-85135 *c
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 36 of 41 figure 9. 44-pin 10 10 1.4 mm tqfp package outline 51-85064 *g
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 37 of 41 acronyms table 43. acronyms used in this document acronym description abus analog local bus adc analog-to-digital converter ag analog global ahb amba (advanced microcontroller bus archi- tecture) high-performance bus, an arm data transfer bus alu arithmetic logic unit amuxbus analog mu ltiplexer bus api application programming interface apsr application program status register arm ? advanced risc machine, a cpu architecture atm automatic thump mode bw bandwidth can controller area network, a communications protocol cmrr common-mode rejection ratio cpu central processing unit crc cyclic redundancy check, an error-checking protocol dac digital-to-analog converter, see also idac, vdac dfb digital filter block dio digital input/output, gpio with only digital capabilities, no analog. see gpio. dmips dhrystone million instructions per second dma direct memory access, see also td dnl differential nonlinearity, see also inl dnu do not use dr port write data registers dsi digital system interconnect dwt data watchpoint and trace ecc error correcting code eco external crystal oscillator eeprom electrically erasable programmable read-only memory emi electromagnetic interference emif external memory interface eoc end of conversion eof end of frame epsr execution program status register esd electrostatic discharge etm embedded trace macrocell fir finite impulse resp onse, see also iir fpb flash patch and breakpoint fs full-speed gpio general-purpose input/output, applies to a psoc pin hvi high-voltage interrupt, see also lvi, lvd ic integrated circuit idac current dac, see also dac, vdac ide integrated development environment i 2 c, or iic inter-integrated circuit, a communications protocol iir infinite impulse response, see also fir ilo internal low-speed oscillator, see also imo imo internal main oscillator, see also ilo inl integral nonlinearity, see also dnl i/o input/output, see also gpio, dio, sio, usbio ipor initial power-on reset ipsr interrupt program status register irq interrupt request itm instrumentation trace macrocell lcd liquid crystal display lin local interconnect network, a communications protocol. lr link register lut lookup table lvd low-voltage detect, see also lvi lvi low-voltage interrupt, see also hvi lvttl low-voltage transistor-transistor logic mac multiply-accumulate mcu microcontroller unit miso master-in slave-out nc no connect nmi nonmaskable interrupt nrz non-return-to-zero nvic nested vectored interrupt controller nvl nonvolatile latch, see also wol opamp operational amplifier pal programmable array logic, see also pld pc program counter pcb printed circuit board table 43. acronyms us ed in this document (continued) acronym description
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 38 of 41 pga programmable gain amplifier phub peripheral hub phy physical layer picu port interrupt control unit pla programmable logic array pld programmable logic device, see also pal pll phase-locked loop pmdd package material declaration data sheet por power-on reset pres precise power-on reset prs pseudo random sequence ps port read data register psoc ? programmable system-on-chip? psrr power supply rejection ratio pwm pulse-width modulator ram random-access memory risc reduced-instruct ion-set computing rms root-mean-square rtc real-time clock rtl register transfer language rtr remote transmission request rx receive sar successive approximation register sc/ct switched capaci tor/continuous time scl i 2 c serial clock sda i 2 c serial data s/h sample and hold sinad signal to noise and distortion ratio sio special input/output, gpio with advanced features. see gpio. soc start of conversion sof start of frame spi serial peripheral interface, a communications protocol sr slew rate sram static random access memory sres software reset swd serial wire debug, a test protocol swv single-wire viewer td transaction descriptor, see also dma table 43. acronyms used in this document (continued) acronym description thd total harmonic distortion tia transimpedance amplifier trm technical reference manual ttl transistor-transistor logic tx transmit uart universal asynchronous transmitter receiver, a communications protocol udb universal digital block usb universal serial bus usbio usb input/output, psoc pins used to connect to a usb port vdac voltage dac, see also dac, idac wdt watchdog timer wol write once latch, see also nvl wres watchdog timer reset xres external reset i/o pin xtal crystal table 43. acronyms us ed in this document (continued) acronym description
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 39 of 41 document conventions units of measure table 44. units of measure symbol unit of measure c degrees celsius db decibel ff femto farad hz hertz kb 1024 bytes kbps kilobits per second khr kilohour khz kilohertz k ? kilo ohm ksps kilosamples per second lsb least significant bit mbps megabits per second mhz megahertz m ? mega-ohm msps megasamples per second a microampere f microfarad h microhenry s microsecond v microvolt w microwatt ma milliampere ms millisecond mv millivolt na nanoampere ns nanosecond nv nanovolt ? ohm pf picofarad ppm parts per million ps picosecond s second sps samples per second sqrthz square root of hertz vvolt
psoc ? 4: psoc 4100m family datasheet document number: 001-96519 rev. *e page 40 of 41 revision history description title: psoc ? 4: psoc 4100m family datasheet programmable system-on-chip (psoc ? ) document number: 001-96519 revision ecn orig. of change submission date description of change *a 4765455 wka 05/20/2015 release to web. *b 4815539 wka 06/29/2015 removed note regarding hardware handshaking in the uart mode section. changed max value of sid51a to 2 ms. added ?guaranteed by characterization? note for sid65 and sid65a updated ordering information. *c 4941619 wka 09/30/2015 updated capsense section. updated the note at the end of the pinout table. removed conditions for spec sid237. *d 5026805 wka 11/26/2015 added comparator ulp mo de range restrictions and corrected typos. *e 5408936 wka 08/19/2016 added extended industrial temperature range. added specs sid290q, sid182a, and sid299a. updated conditions for sid290, sid223, and sid237. added 44-pin tqfp package details. updated ordering information
document number: 001-96519 rev. *e revised august 19, 2016 page 41 of 41 psoc ? 4: psoc 4100m family datasheet ? cypress semiconductor corporation, 2015-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in th is document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, mo dification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but no t limited to, the implied warranties of me rchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of w eapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or propert y damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete lis t of cypress trademarks, visit cypress.com. other names and bran ds may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypess.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions cypress.com/psoc psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/support

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